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Calculating CPU cache hits

发布于 2020-11-21 17:14:06

I am struggling to understand what the process/formula is for calculating cache hits. So, if for example if we have a main memory with 16 entries and a cache memory of 4 entries and the CPU loads the memory addresses: 0, 1, 2, 8, 9, 2’, how can I calculate the number of hits a) if the cache is direct-mapped and b) 2-way associative?

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pio 2020-11-30 21:38:31

Assuming no prefetchers and LRU as the replacing mechanism.

a) For direct-mapped cache, each memory entry can be only in one cache entry. The cache will map like this (default assuming uniform distribution):

Cache 0 --> can hold 0,4,8,12 of the main memory entries.
Cache 1 --> can hold 1,5,9,13 of the main memory entries.
Cache 2 --> can hold 2,6,10,14 of the main memory entries.
Cache 3 --> can hold 3,7,11,15 of the main memory entries.

After reset, the cache is empty.

Load from 0 will be missed and will be cached in cache entry 0.
Load from 1 will be missed and will be cached in cache entry 1.
Load from 2 will be missed and will be cached in cache entry 2.
Load from 8 will be missed and will be cached in cache entry 0 (replaced load 0).
Load from 9 will be missed and will be cached in cache entry 1 (replaced load 1).
load from 2 will be hit and will be taken from cache entry 2.

so we have 1 hit and and 5 misses, the hit rate is 1/(5+1) = 1/6 = 16%

b) For 2 ways associative, you will have for each entry in the memory 2 entries in the cache to go to. so set0 (entries 0,1 in the cache) will hold all the even main memory entries and set1 will hold all the odd entries, so if we span it we will have like this:

cache 0 (set 0) --> can hold 0,2,4,6,8,10,12,14 of the main memory entries.
cache 1 (set 0) --> can hold 0,2,4,6,8,10,12,14 of the main memory entries.
cache 2 (set 1) --> can hold 1,3,5,7,9,11,13,15 of the main memory entries.
cache 2 (set 0) --> can hold 1,3,5,7,9,11,13,15 of the main memory entries.

After reset the cache is empty.

Load from 0 will be missed and will be cached in cache entry 0.
Load from 1 will be missed and will be cached in cache entry 2.
Load from 2 will be missed and will be cached in cache entry 1.
Load from 8 will be missed and will be cached in cache entry 0 (replaced load 0 because we replace the Least Recently Used).
Load from 9 will be missed and will be cached in cache entry 3.
load from 2 will be hit and will be taken from cache entry 1.

in this case the hit rate is the same: 1/(5+1) = 1/6 = 16%