How to use make file functions with $@ to generate prerequisites?

The short answer is, you can't. Automatic variables, as made clear in the documentation, are only set inside the recipe of a rule, not when expanding the prerequisites. There are advanced features you can take advantage of to work around this, but they are intended only to be used in very complicated situations which this isn't, really.

What you want to do is exactly what pattern rules were created to support:

all: $(TARS)

z%: z%.o z.c
        gcc -c -o $@ $^

That's all you need.

ETA

GNU make doesn't provide any completion capabilities, so you'll need to figure out where that completion is done and how it works, to know what you need to have in your makefile to have it work. If it only completes on explicit targets, you can either just make them like this:

all: $(TARS)

$(TARS):

z%: z%.o z.c
        gcc -c -o $@ $^

Or you can use static pattern rules instead:

all: $(TARS)

$(TARS): z%: z%.o z.c
        gcc -c -o $@ $^

I didn't understand the last sentence in your comment below.