我有一个关于Verilog SRAM存储器实现的问题。该模块sram_1port
应该是具有读使能信号和写使能信号的时钟地址可寻址SRAM存储器。该模块control_sram
应该在SRAM中读取/写入数据。数据连续存储在连续的存储器地址中。当我尝试模拟电路行为时会出现问题,因此rd_data
在整个模拟过程中信号不确定。因此,无法输出内存内容,我什至不知道为什么。存储数据时或应该输出内容时,还是两者都有问题时,是否存在问题?
module sram_1port(
input clk,
input [15:0] address,
input wr,rd,
input [2:0] wr_data,
output reg [2:0] rd_data
);
reg [2:0] mem_reg [15:0];
always @ (posedge clk) begin
if(wr) mem_reg[address] <= wr_data;
else if(rd) rd_data <= mem_reg[address];
end
endmodule
//automaton
module control_sram(
input clk, wr, rd,
input [2:0] wr_data,//read 1 instruction/clk
output [2:0] rd_data,//output
output reg [15:0] out//outputs address
);
reg [15:0] address,address_rd,address_wr;
initial address = 16'd0;
initial address_wr = 16'd0;
initial address_rd = 16'd0;
sram_1port i0(.clk(clk),.address(address),.wr(wr),
.rd(rd),.wr_data(wr_data),.rd_data(rd_data));
always @(posedge clk) begin
if(wr) begin
address_wr = address_wr + 1;
address = address_wr;
address_rd = 16'd0;
end
else if(rd) begin
address_rd = address_rd + 1;
address = address_rd;
address_wr = 16'd0;
end
end
always @ * out = address;
endmodule
//tb for control_sram
module control_sram_tb(
output reg clk,wr,rd,
output reg [2:0] wr_data,
output [2:0] rd_data,
output [15:0] out
);
control_sram cut(.clk(clk),.wr(wr),.rd(rd),.wr_data(wr_data),
.rd_data(rd_data),.out(out));
initial $dumpvars(0,control_sram_tb);
initial begin
clk = 1'd1;
repeat (260000)
#100 clk = ~clk;
end
initial begin
wr_data = 3'd1;
#3000000 wr_data = 3'd2;
#1000000 wr_data = 3'd1;
#3000000 wr_data = 3'd0;
#2000000 wr_data = 3'd3;
#1000000 wr_data = 3'd1;
end
initial begin
rd = 1'b0;
#13000000 rd = 1'b1;
end
initial begin
wr = 1'b1;
#13000000 wr = 1'b0;
end
endmodule
运行模拟时,我看到rd_data
在时间13_000_200ns处从X变为1,并且在3_000ns处从1保持为1,然后返回X。你应该看到,如果将波形放大到该时间间隔。如果你看不到icarus,请使用不同的模拟器在edaplayground上运行模拟。
另外,你声明内存(mem_reg
)具有16个位置([15:0]
)。但是,我认为你的address
读写操作采用17、18、19等值。你想访问内存中没有的位置似乎很奇怪。进行读取时,你得到X(按预期)。似乎你只需要一个4位地址,而不需要一个16位地址。
我以为[2:0] mem_reg [15:0]分配2 ^(15-0 + 1)项,每个3位。谢谢!